1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of fabricating a dual damascene interconnection capable of efficiently forming a dual damascene structure having a high aspect ratio especially well suited for applications in highly integrated semiconductor devices without a profile failure. The present invention also relates to an etchant composition for stripping a sacrificial layer in performing a dual damascene process such as in the present invention.
2. Description of the Related Art
With rapid progress and development in the techniques available to produce high-speed, highly-integrated logic devices, new techniques for fabrication of miniaturized transistors have been developed. As the integration level of the transistors has increased, interconnections have become smaller and smaller. As a result, a problem of interconnection delay may become more serious and result in impeding attainment of high-speed logic devices.
Under such a situation, instead of using an aluminum alloy, which has been conventionally and generally used in interconnecting large scale integrated (LSI) semiconductor devices, interconnections using copper, which has the properties of lower resistance and higher electromigration (EM) tolerance as an interconnection material, have been actively developed. However, there are also problems with this approach in that copper is not easy to etch and is prone to oxidation. Accordingly, a damascene process is necessarily employed to form a copper interconnection.
The damascene process is a filling process that typically includes the steps of forming a trench having an upper interconnection formed on an insulating layer, forming a via that connects the upper interconnection to a lower interconnection or to a substrate such that the trench is aligned over the via, filling the trench and the via with copper, and finally planarizing by a chemical mechanical polishing (CMP) process.
Moreover, the use of an insulating layer with a low dielectric constant (hereinafter, referred to as a low-k dielectric) and the copper interconnection reduce parasitic capacitance between interconnections, thereby increasing the speed of the resulting semiconductor devices and reducing crosstalk of the semiconductor devices. At present, development of a variety of low-k dielectrics useful in such applications is under way. The low-k dielectrics are largely divided into SiO2-based inorganic polymers and C-based organic polymers.
Because the strength of the low-k dielectric is typically relatively low, it is likely that the low-k dielectric will be denatured during a process step subsequent to the dual damascene process. Accordingly, a capping layer may be formed on top of the low-k dielectric in order to prevent the denaturation of the low-k dielectric.
A dual damascene process may be employed in forming bit lines or word lines in addition to metal wirings. In particular, in the dual damascene process, vias for connecting an upper metal wiring to a lower metal wiring in a multi-layered metal wiring structure can be formed at the same time. Further, utilizing a dual damascene process facilitates certain process steps subsequent to the dual damascene process because a step difference caused by the metal wiring is removed during the dual damascene process.
A dual damascene process may be either a via-first process or a trench-first process. In the via-first process, a via is first formed by etching a dielectric by photography and etching, and a trench is then formed on top of the via by further etching of the dielectric. In the trench-first process, on the other hand, the trench is first formed and the via is then formed. Of these two approaches, the via-first process is used more often.
A method of forming an interconnection using a dual damascene process is disclosed in U.S. Pat. No. 6,057,239, which patent is incorporated herein by reference. In U.S. Pat. No. 6,057,239, hydrogen silsesquioxane (HSQ) or SOG is used as a sacrificial layer for etching a trench using an oxide layer as an intermetal dielectric. Also, in the disclosed patent, a method of removing the remaining HSQ or SOG after etching a trench using buffered-oxide etch (BOE) or hydrofluoric (HF) solution is described. However, BOE or HF solution can easily penetrate into an interface between a capping layer for preventing deformation of the intermetal dielectric and the intermetal dielectric disposed under the capping layer so that an undercut is thereby generated and the capping layer is lifted up damaging the semiconductor device.
FIG. 1 is a scanning electron microscope (SEM) image photograph showing a capping layer (identified as CAP) and an intermetal dielectric (IMD) after a step of wet etching a sacrificial layer such as HSQ using HF solution. As shown in FIG. 1, an undercut having a size of about 300-400 Å is generated under the capping layer CAP by wet etching the intermetal dielectric IMD (for example HSQ) using HF solution. Also, it can be observed that the intermetal dielectric IMD was inwardly etched and curved at the lower portion of the undercut by wet etching using HF solution. Some prior art in the field, such as U.S. Pat. No. 6,297,149, which patent is incorporated herein by reference, teaches depositing a protective barrier layer within a via after via formation and prior to filling the via with a sacrificial material so as to prevent lateral etching of the via during removal of sacrificial material. It is difficult, however, to deposit an effective diffusion barrier metal or a seed layer on a sidewall of a via or a trench for performing a damascene process in the inwardly curved portion of the intermetal dielectric IMD using any conventional deposition techniques.
These and other problems with and limitations of the prior art technologies in this field are addressed in whole or at least in part by the methods and compositions of this invention.